//-----------------------------------------------
//    module name: 
//    author: Liang
//  
//    version: 1st version (2021-10-01)
//    description: 
//        
//
//
//-----------------------------------------------
`timescale 1ns / 1ps
module timer_slot(
    input  wire         clk,
    input  wire         rstn,
    output wire [ 4:0]  int_sig_o,
    
    output wire         outR         ,
    input  wire         inR          ,
    output wire [50:0]  data_to      ,
    input  wire [50:0]  data_from    ,
    output wire         inA          ,
    input  wire         outA
    );
    
    wire           we;
    wire [31:0]    addr_i;
    wire [31:0]    data_i;
    wire [31:0]    data_o;
    wire clk_perip_slot,clk_timer_module;
`ifdef DC_ClKTREE 
    `CLKBUFF buf_clk_11 (.A(clk),.Z(clk_perip_slot));
    `CLKBUFF buf_clk_12 (.A(clk),.Z(clk_timer_module));
`else
    assign  clk_perip_slot = clk;
    assign  clk_timer_module = clk;
`endif

     perip_slot slot(

        .clk        (clk_perip_slot    ),
        .rstn       (rstn              ),
					
        .outR       (outR              ),
        .inR        (inR               ),
        .data_to    (data_to           ),
        .data_from  (data_from         ),
        .inA        (inA               ),
        .outA       (outA              ),
                    
        .we         (we                ),
        .addr_i     (addr_i            ),
        .data_i     (data_i            ),
        .data_o     (data_o            )
    
    );
    timer_module timer_module(
        .clk        (clk_timer_module  ),
        .rstn       (rstn              ),
        .we_i       (we                ),
        .addr_i     (addr_i            ),
        .data_i     (data_i            ),
        .data_o     (data_o            ),
        .int_sig_o  (int_sig_o         )
    );

    
endmodule
